Making CSB+-Tree Processor Conscious

Michael Samuel, Anders Uhl Pedersen, Philippe Bonnet

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Abstract

Cache-conscious indexes, such as CSB+-tree, are sensitive to the underlying processor architecture. In this paper, we focus on how to adapt the CSB+-tree so that it performs well on a range of different processor architectures. Previous work has focused on the impact of node size on the performance of the CSB+-tree. We argue that it is necessary to consider a larger group of parameters in order to adapt CSB+-tree to processor architectures as different as Pentium and Itanium. We identify this group of parameters and study how it impacts the performance of CSB+-tree on Itanium 2. Finally, we propose a systematic method for adapting CSB+-tree to new platforms. This work is a first step towards integrating CSB+-tree in MySQL’s heap storage manager.
Original languageEnglish
Title of host publicationFirst International Workshop on Data Management on New Hardware
Number of pages6
PublisherACM
Publication date2005
Publication statusPublished - 2005

Keywords

  • Faculty of Science
  • storage management
  • cache conscious processing

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